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gennum corporation p.o. box 489, stn. a, burlington, ontario, canada l7r 3y3 tel. +1 (905) 632-2996 fax. +1 (905) 632-5946 e-mail: info@gennum.com www.gennum.com revision date: august 2005 document no. 522 - 75 - 05 data sheet gs9025a features ? smpte 259m compliant ? operational to 540mb/s ? automatic cable equalizati on (typically greater than 350m of high quality cable at 270mb/s) ? adjustment-free operation ? auto-rate selection (5 rates) with manual override ? single external vco resist or for operation with five input data rates ? data rate indi cation output ? serial data outputs muted and serial clock remains active when input data is lost ? operation independent of sav/eav sync signals ? signal strength indicator output ? carrier detect with programmable threshold level ? power savings mode (out put serial clock disable) ? pb-free and green applications cable equalization plus clock and data recovery for all high speed serial digital interface applications involving smpte 259m and other data standards. description the gs9025a provides automatic cable equalization and high performance clock and data recovery for serial digital signals. the gs9025a receiv es either single-ended or differential serial digital data and outputs differential clock and retimed data signals at pecl levels (800mv). the on- board cable equalizer provides up to 40db of gain at 200mhz which typically results in equalization of greater than 350m of high qual ity cable at 270mb/s. the gs9025a operates in either auto or manual data rate selection mode. in both modes, the gs9025a requires only one external resistor to set the vco centre frequency and provides adjustment free operation. the gs9025a has dedicated pins to indicate signal strength/carrier detect, lo ck and data rate. optional external resistors allow the carrier detect threshold level to be customized to the user's requirement. in addition, the gs9025a provides an 'output eye monitor test' (oem_test) for diagno stic testing of signal integrity after equalization, prior to reslicing. the serial clock outputs can also be disabled to reduce power. the gs9025a operates from a single +5 or -5 volt supply. block diagram ordering information part number package temperature pb-free and green gs9025acqm 44 pin mqfp tray 0c to 70c no gs9025actm 44 pin mqfp tape 0c to 70c no GS9025ACQME3 44 pin mqfp tray 0c to 70c yes gs9025actme3 44 pin mqfp tape 0c to 70c yes lf+ lfs lf- cbg r vco carrier detect phaselock harmonic frequency acquisition vco division 3 bit counter lock sdo sdo clk_en sco sco smpte auto/man ss0 ss1 ss2 mute c osc a/d phase detector decoder logic analog digital mux ddi + - ddi sdi sdi oem_test agc cap cd_adj auto eq control eye monitor variable gain eq stage charge pump + - + - ssi/cd genlinx ? ii gs9025a serial digital receiver
gennum corporation 522 - 75 - 05 2 of 18 gs9025a absolute maximum ratings parameter value supply voltage (v s )5.5v input voltage range (any input) v cc + 0.5 to v ee - 0.5v operating temperature range 0c t a 70c storage temperature range -65c t s 150c lead temperature (soldering, 10 sec) 260c dc electrical characteristics v cc = 5.0v, t a = 0 to 70c unless otherwise stated, r lf = 1.8k, c lf1 = 15nf, c lf2 = 3.3pf parameter condition min typical 1 max units notes test level supply voltage 4.75 5 5.25 v 3 supply current clk_en = 0 - 115 ma 9 clk_en = 1 - 125 ma 3 sdi common mode voltage - 2.4 - v 3 ddi common mode input voltage range v ee +(v diff /2) 0.4 to 4.6 v cc -(v diff /2) v 2 3 ddi differential input drive 200 800 2000 mv 3 ssi/cd output current high, 100m, 143mb/s, oh =-10a -4.2-v 3 high, 300m, 143mb/s, oh =-10a -3.7- low, ol =1ma - 0.4 0.8 v 1 oem_test bias potential r l =50 -4.75-v53 a/d high 2.3 - - v 3 low - - 0.8 auto/man, smpte, ss[2:0] input voltage high 2.0 - - v 3 low - - 0.8 clk_en input voltage high 2.5 - - v 3 low - - 0.8 lock output low voltage ol =500a - 0.25 0.4 v 3 1 ss[2:0] output voltage high, oh =-180a, auto mode 4.4 4.8 - v 1 low, ol =600a, auto mode - 0.3 0.4
gennum corporation 522 - 75 - 05 3 of 18 gs9025a ss[2:0] input voltage high, manual mode 2 - - v 3 low, manual mode - - 0.8 clk_en source current low, v il = 0v - 26 55 a 1 notes 1. typical - measured on eb9025a board. 2. v diff is the differential input signal swing. 3. lock is an open collector output and requires an external pull-up resistor. 4. pins ss[2:0] are outputs in auto mode and inputs in manual mode. 5. if oem_test is permanently enabled, operating temperature range is limited from 0c to 60c inclusive. test levels 1. production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges. 2. production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges using correlated test. 3. production test at room temperature and nominal supply voltage. 4. qa sample test. 5. calculated result based on level 1,2, or 3. 6. not tested. guaranteed by design simulations. 7. not tested. based on characterization of nominal parts. 8. not tested. based on existi ng design/characterization data of similar product. 9. indirect test. ac electrical characteristics v cc = 5.0v, v ee = 0v, t a = 0 to 70c unless otherwise stated, r lf = 1.8k, c lf1 = 15nf, c lf2 = 3.3pf parameter conditions min typical 1 max units notes test level serial data rate sdi 143 - 540 mb/s 3 maximum equalizer gain @ 200mhz - 40 - db 6 additive jitter [pseudorandom (2 23 -1)] 270mb/s, 300m (belden 8281) - 300 - ps p-p 2, 8 9 540mb/s, 100m (belden 8281) - 275 - intrinsic jitter [pseudorandom (2 23 -1)] 270mb/s - 185 see figure 12 ps p-p 2, 7 4 540mb/s - 164 intrinsic jitter [pathological (sdi checkfield)] 270mb/s - 462 see figure 13 ps p-p 2, 7 3 360mb/s - 308 540mb/s - 260 input jitter tolerance 270mb/s 0.40 0.56 - ui p-p 3, 7 9 540mb/s 0.32 0.43 - lock time - synchronous switch t switch < 0.5s, 270mb/s - 1 - s 4 7 0.5s< t switch <10ms - 1 - ms t switch > 10 ms - 4 - ms lock time - asynchronous switch loop bandwidth = 6mhz @ 540mb/s -10 - ms 57 dc electrical characteristics (continued) v cc = 5.0v, t a = 0 to 70c unless otherwise stated, r lf = 1.8k, c lf1 = 15nf, c lf2 = 3.3pf parameter condition min typical 1 max units notes test level
gennum corporation 522 - 75 - 05 4 of 18 gs9025a fig. 1 test setup for figures 6 - 13 sdo mute time 0.5 1 2 s 6 7 sdo to sco synchronization -200 0 200 ps 7 sdo, sco output signal swing 75 dc load 600 800 1000 mv p-p 1 sdo, sco rise & fall times 20%-80% 200 300 400 ps 7 sdi/sdi input resistance - 10 - k 86 sdi/sdi input capacitance - 1.0 - pf 8 6 carrier detect response ti me carrier applied, - 3 - s 8, 9 6 carrier removed, - 30 - notes 1. typical - measured on cb9025a board. 2. characterized 6 sigma rms. 3. ijt measured with sinusoidal modulation beyond loop bandwidth (at 6.5mhz). 4. synchronous switching refers to switching the input data from one source to another source which is at the same data rate (ie. line 10 switching for component ntsc). 5. asynchronous switching refers to switching the input data from one source to another source which is at a different data rate. 6. sdo mute time refers to the response of the sdo outputs from valid re-clocked input data to mute mode when the input signal is removed. 7. using the ddi input, a/d =0. 8. using the sdi input, a/d =1. 9. carrier detect response time refe rs to the response of the ssi/cd output from a logic high to logic low state when the input signal is removed or its amplitude drops below the threshold set by the cd_adj pin. ssi/cd pin loading c l <50 p f, r l = open cct. test levels 1. production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges. 2. production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges using correlated test. 3. production test at room temperature and nominal supply voltage. 4. qa sample test. 5. calculated result based on level 1,2, or 3. 6. not tested. guaranteed by design simulations. 7. not tested. based on characterization of nominal parts. 8. not tested. based on existing design/characterization data of similar product. 9. indirect test. ac electrical characteristics (continued) v cc = 5.0v, v ee = 0v, t a = 0 to 70c unless otherwise stated, r lf = 1.8k, c lf1 = 15nf, c lf2 = 3.3pf parameter conditions min typical 1 max units notes test level cb9025a board gs9028 cable driver tektronix gigabert 1400 analyzer tektronix gigabert 1400 transmitter belden 8281 cable data data clock trigger
gennum corporation 522 - 75 - 05 5 of 18 gs9025a pin connections pin descriptions number symbol type description 1, 2 ddi/ddi i digital data inputs (differential ecl/pecl). 3, 44 v cc _75 i power supply connection for internal 75 pull-up resistors connected to ddi/ddi . 4, 8, 13, 22, 35 v cc i most positive power supply connection. 5, 9, 14, 18, 27, 30, 33, 34, 37 v ee i most negative power supply connection. 6, 7 sdi/sdi i differential analog data inputs. 10 cd_adj i carrier detect threshold adjust. 11, 12 agc-, agc+ i external agc capacitor. v common mode =2.7v typ. 15 lf+ i loop filter component connection. 16 lfs i loop filter component connection. 17 lf- i loop filter component connection. 19 r vco _rtn i frequency setting resistor return connection. 20 r vco i frequency setting resistor connection. 21 cbg i internal bandgap voltage filter capacitor. 23, 24, 25 ss[2:0] i/o data rate indication (auto mode) or data rate select (manual mode). ttl/cmos compatible i/o. in auto mode, these pins can be left unconnected. 26 auto/man i auto or manual mode select. ttl/cmos compatible input. sdo sdo v ee sco sco v ee auto/man ss0 ss1 ss2 gs9025a top view agc+ v cc v ee lf+ lfs lf- v ee r vco _rtn r vco cbg v cc ddi ddi v cc _75 v cc v ee sdi sdi v cc v ee cd_adj agc- v cc _75 oem_test smpte a/d ssi/cd lock c osc v ee clk_en v cc v ee v ee 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34
gennum corporation 522 - 75 - 05 6 of 18 gs9025a 28, 29 sco /sco o serial clock output. sco /sco are differential current mode outputs and require external 75 pull-up resistors. 31, 32 sdo /sdo o equalized and reclocked se rial digital data outputs. sdo /sdo are differential current mode outputs and require external 75 pull-up resistors. 36 clk_en i clock enable. when high, the serial clock outputs are enabled. 38 c osc i timing control capacitor for internal system clock. 39 lock o lock indication. when high, the gs9025a is locked. lock is an open collector output and requires an external 10k pull-up resistor. 40 ssi/cd o signal strength indicator/carrier detect. 41 a/d i analog/digital select. 42 smpte i smpte/other data rate select. ttl/cmos compatible input. 43 oem_test o output ?eye? monitor te st. single-ended current mode output that requires an external 50 pull-up resistor. this feature is reco mmended for debugging purposes only. if enabled during normal operation, the maximum operating temperature is rated to 60c. for maximum cable length performance oem_test must be disabled. pin descriptions (continued) number symbol type description
gennum corporation 522 - 75 - 05 7 of 18 gs9025a typical performance curves (v s = 5v, t a = 25c unless otherwise shown) fig. 2 ssi/cd voltage vs. cable length (belden 8281) (cd_adj = 0v) fig. 3 equalizer gain vs. frequency fig. 4 carrier detect adjust voltage threshold characteristics fig. 5 input impedance fig. 6 typical additive jitter vs. input cable length (belden 8281) pseudorandom (2 23 -1) fig. 7 typical error free cable length 0 50 100 150 200 250 300 350 400 450 500 5.00 4.50 4.00 3.50 3.00 2.50 cable length (m) ssi/cd output voltage (v) 0 5 10 15 20 25 30 35 40 45 50 1 10 100 1000 gain (db) frequency (mhz) 5.0 4.5 4.0 3.5 3.0 2.5 2.0 200 250 300 350 400 cable length (m) cd_adj voltage (v) 270 j1 3000 1620 810 -j1 -j2 -j5 j5 j2 j0.2 -j0.2 -j0.5 j0.5 frequencies in mhz, impedances normalized to 50 jitter (ps p-p) cable length (m) 450 400 350 300 250 200 150 100 50 0 0 50 100 150 200 250 300 350 400 540mb/s 270mb/s (characterized) cable length (m) data rate (mb/s) 100 450 400 350 300 250 200 150 200 300 400 500 600
gennum corporation 522 - 75 - 05 8 of 18 gs9025a fig. 8 intrinsic jitter (2 23 - 1 pattern) 30mb/s fig. 9 intrinsic jitter (2 23 - 1 pattern) 143mb/s fig. 10 intrinsic jitter (2 23 - 1 pattern) 270mb/s fig. 11 intrinsic jitter (2 23 - 1 pattern) 540mb/s fig. 12 intrinsic jitter - pseudorandom (2 23 - 1) fig. 13 intrinsic jitter - pathological sdi checkfield 0 200 400 600 800 1000 1200 1400 1600 1800 2000 100 200 300 400 500 600 sdi data rate (mb/s) jitter (ps) max typical min t a =0 to 70?c, v cc =4.75 to 5.25v for the typical range typical range, characterized 0 200 400 600 800 1000 1200 1400 1600 1800 2000 100 200 300 400 500 600 sdi data rate (mb/s) typical min jitter (ps p-p) max t a = 0 to 70?c, v cc = 4.75 to 5.25v for the typical range typical range, characterized
gennum corporation 522 - 75 - 05 9 of 18 gs9025a fig. 14 typical input jitter tolerance (characterized) fig. 15 typical ijt vs. temperature (v cc = 5.0v) (characterized) detailed description the gs9025a serial digital rece iver is a bipolar integrated circuit containing a built-in cable equalizer and reclocker. serial digital signals are applied to either the analog sdi/sdi or digital ddi/ddi inputs. signals applied to the sdi/sdi inputs are equalized and then passed to a multiplexer. signals applied to the ddi/ddi inputs bypass the equalizer and go directly to the multiplexer. the analog/digital select pin (a/d ) determines which signal is then passed to the reclocker. packaged in a 44 pin mqfp, the receiver operates from a single 5v supply to data ra tes of 540mb/s. typical power consumption is 575mw. 1. cable equalizer the automatic cable equalizer is designed to equalize serial digital data signals from 143mb/s to 540mb/s. the serial data signal is connected to the input pins (sdi/sdi ) either differentially or single-ended. an input return loss of 20db at 270 mb/s has typically been achieved on the cb9025a characterization board. the input signal then passes through a variable gain equalizing stage whose frequency response closely matches the inverse cable loss characteristic. the variation of the frequency response with control voltage imit ates the variation of the inverse cable loss characteristic with cable length. the gain stage provides up to 40db of gain at 200mhz which typically results in equalizat ion of greater than 350m at 270mb/s of belden 8281 cable. the edge energy of the equalized signal is monitored by a detector circuit which produces an error signal corresponding to the difference between the desired edge energy and the actual edge energy. this error signal is integrated by an external diff erential agc filter capacitor (agc+/agc-) providing a steady control voltage for the gain stage. as the frequency response of the gain stage is automatically varied by th e application of negative feedback, the edge energy of the equalized signal is kept at a constant level which is representative of the original edge energy at the transmitter. the equalized signal is dc re stored, effectively restoring the logic threshold of the equa lized signal to its corrective level irrespective of shif ts due to ac coupling. 1.1 signal strength indication/carrier detect the gs9025a incorporates an analog signal strength indicator/carrier detect (ssi/cd) output indicating both the presence of a carrier and the amount of equalization applied to the signal. the voltage output of this pin versus cable length (signal strength) is shown in figures 2 and 16. with 0m of cable (800mv input signal levels), the ssi/cd output voltage is approximat ely 4.5v. as the cable length increases, the ssi/cd voltage decreases linearly providing accurate correlation between t he ssi/cd voltage and cable length. fig. 16 ssi/cd voltage vs. cable length 0 0.1 0.2 0.3 0.4 0.5 0.6 100 200 300 400 500 600 data rate (mb/s) ijt (ui) t a = 0 to 70?c, v cc = 4.75 to 5.25v 0.200 0.250 0.300 0.350 0.400 0.450 0.500 0.550 0.600 0 10203040506070 temperature (c?) ijt (ui) 143mb/s 177mb/s 270mb/s 360mb/s 540mb/s 0 1 2 3 4 5 50 100 150 200 250 300 350 400 450 500 ssi/cd output voltage (v) cable length (m) 0 cd_adj control range
gennum corporation 522 - 75 - 05 10 of 18 gs9025a when the signal strength decreases to the level set at the "carrier detect threshold adjust" pin, the ssi/cd voltage goes to a logic "0" state (0.8 v) and can be used to drive other ttl/cmos comp atible logic inputs. when loss of carrier is detected, the sdo/sdo outputs are muted (set to a known static state). additional ssi/cd output source current can be obtained in applications with a pull-up resistor. an external 5k pull-up resistor with less than 50pf capacitor loading is recommended. 1.2 carrier detect threshold adjust carrier detect threshold adjust is designed for applications such as routers where signal crosstalk and circuit noise cause the equalizer to output erroneous data when no input signal is present. the gs9025a solves this problem with a user adjustable threshol d which meets the unique conditions that exist in each application. override and internal default settings are provided to give the user total flexibility. the threshold level at which loss of carrier is detected is adjustable via external resist ors at the cd_adj pin. the control voltage at the cd_adj pin is set by a simple resistor divider circuit ( see typical application circuit ). the threshold level is adjustable from 200m to 350m. by default (no external resistors), the threshold is typically 320m. in noisy environments, it is not recommended to leave this pin floating. connecting this pin to v ee disables the sdo/sdo muting function and allows for maximum possible cable length equalization. 1.3 output eye monitor test the gs9025a provides an 'output eye monitor test' (oem_test) which allows the ve rification of signal integrity after equalization, prior to reslicing. the oem_test pin is an open collector current output that requires an external 50 pull-up resistor. when the pull-up resistor is not used, the oem_test block is disabled and the internal oem_test circuit is powered down. the oem_test provides a typical 100mv p-p signal when driving a 50 oscilloscope input. due to additional power consumed by this diagnostic circuit, it is not recommended for continuous operation. note: for maximum cable length performance the oem_test block should be disabled. 2. reclocker the reclocker receives a differential serial data stream from the internal multiplexer. it locks an internal clock to the incoming data. it outputs the differential pecl retimed data signal on sdo/sdo . it outputs the recovered clock on sco/sco . the timing between the output and clock signals is shown in figure 17. fig. 17 output and clock signal timing the reclocker contains four main functional blocks: the phase locked loop, frequency acquisition, logic circuit, and auto/manual data rate select. 2.1 phase locked loop (pll) the phase locked loop locks the internal pll clock to the incoming data rate. a simplified block diagram of the pll is shown below. the main comp onents are the vco, the phase detector, the charge pump, and the loop filter. fig. 18 simplified block diagram of the pll 2.1.1 vco the vco is a differential low phase noise, factory trimmed design that provides increased immunity to pcb noise and precise control of the vco centre frequency. the vco operates between 30 and 540mb/s and has a pull range of 15% about the centre frequency. a single low impedance external resistor, r vco , sets the vco centre frequency ( see figure 19 ). the low impedance r vco minimizes thermal noise and reduces the pll's sensitivity to pcb noise. for a given r vco value, the vco can oscillate at one of two frequencies. when smpte = ss 0 = logic 1, the vco centre frequency corresponds to the ? l curve. for all other smpte/ss0 combinations, the vco centre frequency corresponds to the ? h curve (? h is approximately 1.5 x ? l ). sdo sco 50% ddi/ddi lf+ lfs lf- r vco vco division r lf c lf1 c lf2 2 phase detector internal pll clock charge pump loop filter
gennum corporation 522 - 75 - 05 11 of 18 gs9025a fig. 19 r vco vs. vco centre frequency the recommended r vco value for auto rate smpte 259m applications is 365 . the vco and an internal divider generate the pll clock. divider moduli of 1, 2, and 4 allow the pll to lock to data rates from 143mb/s to 540mb/s. the divider modulus is set by the auto/man , smpte, and ss[2:0] pins (for further details, see section 2.4, auto/manual data rate select) . in addition, a manually selectable modulus 8 divider allows operation at data rates as low as 30mb/s. when the input data stream is removed for an excessive period of time (see ac electrical characteristics table), the vco frequency can drift from the previously locked frequency to the limits shown in table1. 2.1.2 phase detector the phase detector compares the phase of the pll clock with the phase of the incoming data signal and generates error correcting timing pulses . the phase detector design provides a linear transfer function which maximizes the input jitter tolerance of the pll. 2.1.3 charge pump the charge pump takes the phase detector output timing pulses and creates a charge packet that is proportional to the system phase error. a uniq ue differential charge pump design ensures that the outpu t phase does not drift when data transitions are sparse. this makes the gs9025a ideal for smpte 259m applications where pathological signals have data transition densities of 0.05. 2.1.4 loop filter the loop filter integrates the charge pump packets and produces a vco control vo ltage. the loop filter is comprised of three external components which are connected to pins lf+, lfs, and lf-. the loop filter design is fully differential which increases the gs9025?s immunity to pcb board noise. the loop filter components are critical in determining the loop bandwidth and damping of the pll. choosing these component values is discussed in detail in section 2.9, pll design guidelines . recommended values for smpte 259m applications are shown in the typical application circuit. 2.2 frequency acquisition the core pll is able to lock if the incoming data rate and the pll clock frequency are within the pll capture range (which is slightly larger than the loop bandwidth). to assist the pll to lock to data rates outside of the capture range, the gs9025a uses a freq uency acquisition circuit. the frequency acquisition circuit sweeps the vco control voltage so that the vco frequency changes from -10% to +10% of the centre frequency. figure 20 shows a typical sweep waveform. fig. 20 typical sweep waveform the vco frequency starts at point a and sweeps up attempting to lock. if lock is not established during the up sweep, the vco is then swept down. the probability of locking within one cycle period is greater than 0.999. if the system does not lock within one cycle peri od, it will attempt to lock in the subsequent cycle. in manual mode, the divider modulus is fixed for all cycles. in auto mode, each subsequent cycle is based on a different divider moduli as determined by the internal 3-bit counter. the average sweep time, t swp , is determined by the loop filter component, c lf1 , and the charge pump current, cp : the nominal sweep time is approximately 121s when c lf1 = 15nf and cp = 165a (r vco = 365 ). an internal system clock determines t sys (see section 2.3, logic circuit) . table 1: frequency drift range (when pll loses lock) loses lock from min (%) max(%) 143mb/s lock -21 21 177mb/s lock -12 26 270mb/s lock -13 28 360 mb/s lock -13 24 540 mb/s lock -13 28 0 100 200 300 400 500 600 700 800 0 200 400 600 800 1000 1200 1400 1600 1800 vco frequency (mhz) r vco ( ) ? h ? l smpte=1 sso=1 v lf t swp t cycle t cycle = t swp + t sys t sys a t swp 4c lf1 3 i cp ---------------- =
gennum corporation 522 - 75 - 05 12 of 18 gs9025a 2.3 logic circuit the gs9025a is controlled by a finite state logic circuit which is clocked by an asynchronous system clock. in other words, the system clock is com pletely indepe ndent of the incoming data rate. it runs at low frequencies, relative to the incoming data rate, thereby reducing interference to the pll. the period of the system clock is set by the c osc capacitor and is the recommended value for t sys is 450s (c osc = 4.7nf). 2.4 auto/manual data rate select the gs9025a can operate in either auto or manual data rate select mode. the mode of operation is selected by a single input pin (auto/man ). 2.4.1 auto mode (auto/man = 1) in auto mode, the gs9025a uses a 3-bit counter to automatically cycle through five (smpte=1) or three (smpte=0) different divider modu li as it attempts to acquire lock. in this mode, the ss[2:0] pins are outputs and indicate the current value of the divider moduli according to table 2. note: for smpte = 0 and divider moduli of 2 and 4, the pll can correctly lock for two values of ss[2:0]. 2.4.2 manual mode (auto/man = 0) in manual mode, the gs9025a divider moduli is fixed. in this mode, the ss[2:0] pins are inputs and set the divider moduli according to table 3. 2.5 locking the gs9025a indicates lock when three conditions are satisfied: 1. input data is detected. 2. the incoming data signal and the pll clock are phase locked. 3. the system is not locked to a harmonic. the gs9025a defines the presence of input data when at least one data transition occurs every 1s. the gs9025a assumes that it is not locked to a harmonic if the pattern ?101? or ?010? (in the reclocked data stream) occurs at least once every t sys /3 seconds. using the recommended component values, this corresponds to approximately 150s. in a harmonically locked system, all bit cells are double clocked and the above patterns become ?110011? and ?001100?, respectively. table 2. auto/man = 1 (auto mode) ? h , ? l = vco centre frequency as per figure 19. smpte ss[2:0] divider moduli pll clock 1 000 4 ? h /4 1 001 2 ? l /2 1 010 2 ? h /2 1 011 1 ? l 1 100 1 ? h 1 101 - - 1 110 - - 1 111 - - 0 000 4 ? h /4 0 001 4 ? h /4 0 010 2 ? h /2 0 011 2 ? h /2 0 100 1 ? h 0 101 - - 0 110 - - 0 111 - - t sys 9.6 10 4 c osc onds sec [] = table 3. auto/man = 1 (manual mode) ? h , ? l = vco centre frequency as per figure 19. smpte ss[2:0] divider moduli pll clock 10004? h /4 10012? l /2 10102? h /2 10111 ? l 11001 ? h 11018? l /8 11108? h /8 1111 - - 00004? h /4 00014? h /4 00102? h /2 00112? h /2 01001 ? h 01011 ? h 01108? h /8 0111 - -
gennum corporation 522 - 75 - 05 13 of 18 gs9025a 2.5.1 lock time the lock time of the gs902 5a depends on whether the input data is switching synchronously or asynchronously. synchronous switching means that the input data is changed from one source to another source which is at the same data rate (but different phase). asynchronous switching means that the input data is changed from one source to another source which is at a different data rate. when input data to the gs9025a is removed, the gs9025a latches the current state of the counter (divider modulus). therefore, when data is reapp lied, the gs9025a begins the lock procedure at the previous locked data rate. as a result, in synchronous switching applications, the gs9025a locks very quickly. the nominal lock time depends on the switching time and is summarized in table 4. in asynchronous switching ap plications, including power up, the lock time is determi ned by the frequency acquisition circuit (see section 2.2, frequency acquisition) . to acquire lock in manual mode, the frequency acquisition circuit may have to sweep over an entire cycle depending on initial conditions. maximum lock time is 2t cycle + 2t sys . to acquire lock in auto tune mode, the frequency acquisition circuit may have to cycle through 5 possible counter states depending on initial conditions. maximum lock time is 6t cycle + 2t sys. the nominal value of t cycle for the gs9025a operating in a typical smpte 259m application is approximately 1.3ms. the gs9025a has a dedicated lock output (pin 39) indicating when the device is locked. note: in synchronous switching applications where the switching time is less than 0.5s, the lock output will not be de-asserted and the data outputs will not be muted. 2.5.2 dvb-asi design note: for dvb-asi applications having significant instances of few bit transitions or when only k28.5 idle bits are transmitted, the wide-band pll in the gs9025a may lock at 243mhz being the first 27mhz sideband below 270mhz. in this case, when normal bit density signals are transmitted, the pll will corre ctly lock onto the proper 270mhz carrier. 2.6 output data muting the gs9025a internally mutes the sdo and sdo outputs when the device is not locked. when muted, sdo /sdo are latched providing a logic state to the subsequent circuit and avoiding a condition wher e noise could be amplified and appear as data. the output data muting timing is shown in figure 21. fig. 21 output data muting timing 2.7 clock enable when clk_en is high, the gs9025a sco /sco outputs are enabled. when clk_en is low, the sco /sco outputs are set to a high z state and float to v cc . disabling the clock outputs results in a powe r savings of 10%. it is recommended that the clk_en input be hard wired to the desired state. for applications which do not require the clock output, connect clk_en to ground and connect the sco /sco outputs to v cc . 2.8 stressful data patterns all pll's are susceptible to stressful data patterns which can introduce bit errors in the data stream. pll's are most sensitive to patterns which have long run lengths of 0's or 1's (low data transition densitie s for a long period of time). the gs9025a is designed to operate with low data transition densities such as the smpte 259m pathological signal (data transi tion density = 0.05). 2.9 pll design guidelines the reclocking performance of the gs9025a is primarily determined by the pll. thus, it is important that the system designer is familiar with the basic pll design equations. a model of the gs9025a pll is shown in figure 22. the main components are the phase detector, the vco, and the external loop filter components. table 4. switching time lock time <0.5s 10s 0.5s - 10ms 2t sys >10ms 2t cycle + 2t sys lock ddi sdo valid data no data transitions valid data outputs muted
gennum corporation 522 - 75 - 05 14 of 18 gs9025a fig. 22 model of the gs9025a 2.9.1 transfer function the transfer function of the pll is defined as ? o /? i and can be approximated as: equation 1 where and n is the divider modulus d is the data density (=0.5 for nrz data) i cp is the charge pump current in amps k ? is the vco gain in hz/v this response has 1 zero (w z ) and three poles (w p1 ,w bw ,w p2 ) where: the bode plot for this transfer function is plotted in figure 23. fig. 23 transfer function bode plot the 3db bandwidth of the transfer function is approximately: 2.9.2 transfer function peaking there are two causes of peakin g in the pll transfer function given by equation 1. the first is the quadratic: which has: and this response is critic ally damped for q = 0.5. thus, to avoid peaking: or therefore, w p2 > 4 w bw to reduce the high frequency content on the loop filter, keep w p2 as low as possible. the second is the zero-pole combination: loop filter ? i ? o vco cp r lf k pd c lf1 c lf2 phase detector 2 k ? + - ns ? o ? i ------ - sc lf1 r lf 1 + sc lf1 r lf l r lf --------- ? ?? ?? 1 + ---------------------------------------------------------------- 1 s 2 c lf2 ls l r lf --------- 1 ++ --------------------------------------------------------- = l n d i cp k ? -------------------- = w z 1 c lf1 r lf ---------------------- - = w p1 1 c lf1 r lf l r lf --------- ? -------------------------------------- - = w bw r lf l --------- = w p2 1 c lf2 r lf ---------------------- - = w z w p1 w bw w p2 frequency amplitude w 3db w bw 12 w bw w p2 ----------- - ? w bw w p2 ? () 2 12 w bw w p2 ----------- - ? --------------------------------- - + ---------------------------------------------------------------------- w bw 0.78 ----------- - = s 2 c lf2 ls l r lf --------- 1 ++ w o 1 c lf2 l -------------------- = qr lf r lf2 l ------------ = r lf c lf2 l ------------ - 1 2 -- - < 1 r lf2 c lf2 ------------------------- - l r lf --------- 4 > sc lf1 r lf 1 + sc lf1 r lf 1 r lf --------- ? ?? ?? 1 + ---------------------------------------------------------- s w z ------ - 1 + s w p1 --------- - 1 + ------------------- - =
gennum corporation 522 - 75 - 05 15 of 18 gs9025a this causes lift in the transfer function given by: to keep peaking to less than 0.05db: w z < 0.0057w bw 2.9.3 selection of loop filter components based on the above analysis, the loop filter components should be selected for a given pll bandwidth, ? 3db , as follows: 1. calculate where: i cp is the charge pump current and is a function of the r vco resistor and is obtained from figure 24. k ? = 90mhz/v for vco frequencies corresponding to the ? l curve. k ? = 140mhz/v for vco frequencies corresponding to the ? h curve. n is the divider modulus (? l , ? h and n can be obtained from table 2 or table 3) 2. choose r lf = 2(3.14)? 3db (0.78)l 3. choose c lf1 = 174l/(r lf ) 2 4. choose c lf2 = l/4(r lf ) 2 fig. 24 r vco vs. charge pump current 2.9.4 spice simulations more detailed analysis of the gs9025a pll can be done using spice. a spice model of the pll is shown below: fig. 25 spice model of the pll the model consists of a voltage controlled current source (g1), the loop filter components (r lf , c lf1 , and c lf2 ), a voltage controlled voltage source (e1), and a voltage source (v1). r2 is necessary to create a dc path to ground for node 1. v1 is used to generate the input phase waveform. g1 compares the input and ou tput phase waveforms and generates the charge pump current, cp . the loop filter components integrate the charge pump current to establish the loop filter voltage. e1 creates the output phase waveform (phio) by multiplyin g the loop filter voltage by the value of the laplace transform (2 k ? /ns). the net list for the model is given below. the .param statements are used to set values for cp , k ? , n, and d. cp is determined by the r vco resistor and is obtained from figure 24. spice netlist * gs9025a pll model .param icp = 165e-6 kf= 90e+6 .param n = 1 d = 0.5 .param pi = 3.14 .ic v(phio) = 0 .ac dec 30 1k 10meg rlf 1 lf 1000 clf1 1 0 15n clf2 0 lf 15p e_laplace1 phio 0 laplace {v(lf)} {(2*pi*kf)/(n*s)} g1 0 lf value{d * icp/(2*pi)*v(phii, phio)} v1 2 0 dc 0v ac 1v r2 0 1 1g .end 20 log w p1 w z --------- - 20 log 1 1 w z w bw ----------- - ? --------------------- = l 2n i cp k ? --------------- = 0 50 100 150 200 250 300 350 400 0 200 400 600 800 1000 1200 1400 1600 1800 charge pump current (a) r vco ( ) phii phio r2 e1 r lf c lf1 c lf2 g1 v1 2 k ? in+ in- ns 1 lf note: phii, phio, lf, and 1 are node names in the spice netlist.
gennum corporation 522 - 75 - 05 16 of 18 gs9025a 3. i/o description 3.1 high speed analog inputs (sdi/sdi ) sdi/sdi are high impedance inputs which accept differential or single-ended input drive. figure 26 shows the recommended interface when a single- ended serial digital signal is used. fig. 26 3.2 high speed digital inputs (ddi/ddi ) ddi/ddi are high impedance inputs which accept differential or single-ended input drive. two conditions must be observed when interfacing to these inputs: 1. input signal am plitudes are between 200 and 2000mv. 2. the common mode input voltage range is as specified in the dc characteristics table. commonly used interface examples are shown in figures 27 to 29. figure 27 illustrates the simplest interface to the gs9025a digital inputs. in this example, the driving device generates the pecl level signals ( 800mv amplitudes) having a common mode input range be tween 0.4v and 4.6v. this scheme is recommended when the trace lengths are less than 1in. the value of the resistors depends on the output driver circuitry. fig. 27 when trace lengths become greater than 1in, controlled impedance traces should be used. the recommended interface is shown in figure 29. in this case, a parallel resistor (r load ) is placed near the gs9025a inputs to terminate the controlled impedance trace. the value of r load should be twice the value of the characteristic impedance of the trace. in ad dition, place series resistors (r source ) near the driving chip to serve as source terminations. they should be equal to the value of the trace impedance. assuming 800mv out put swings at the driver, r load = 100 , r source = 50 and z o = 50 . fig. 28 figure 29 shows the recommended interface when the gs9025a digital inputs are driven single-endedly. in this case, the input must be ac-coupled and a matching resistor (z o ) must be used. fig. 29 when the ddi and the ddi inputs are not used, saturate one input of the differential amplifier for improved noise immunity. to saturate, connect either pins 44 and 1 or pins 2 and 3 to v cc . leave the other pair floating. 3.3 high speed outputs (sdo/sdo and sco/sco ) sdo/sdo and sco/sco are current mode outputs that require external pullup resistors ( see figure 30 ). to calculate the output sink current use the following relationship: output sink current = output signal swing / pullup resistor a diode can be placed between v cc and the pullup resistors to reduce the common mode voltage by approximately 0.7 volts. when the output traces are longer than 1in, controlled impedance traces should be used. the pullup resistors should be placed at the end of the output traces as they terminate the trace in its characteristic impedance (75 ). fig. 30 high speed outputs with external pullups 4. optimizing gs9025a performance for optimal device performa nce, implement loop filter component values for the gs9025a as shown in table 5. sdi gs9025 sdi 75 10nf 10nf 75 113 ddi ddi gs9025 table 5: recommended loop filter component values component gs9025 gs9025a r lf 1k 1.8k c lf1 15nf 15nf c lf2 5.6pf 3.3pf ddi ddi r source r load r source z o z o gs9025 ddi ddi z o gs9025 v cc sdo sdo sco sco 75 75 v cc 75 75 gs9025
gennum corporation 522 - 75 - 05 17 of 18 gs9025a typical application circuit table 6: r vco = 365, ? h = 540mhz, ? l = 360mhz smpte ss[2:0] data rate (mb/s) loop bandwidth (mhz) 1 000 143 1.2 1 001 177 1.9 1 010 270 3.0 1 011 360 4.5 1 100 540 6.0 sdo sdo v ee sco sco v ee ss0 ss1 ss2 gs9025a top view agc+ v cc v ee lf+ lfs lf- v ee r vco _rtn r vco cbg v cc ddi ddi v cc_75 v cc v ee sdi sdi v cc v ee cd_adj agc- v cc_75 oem_test smpte a/d ssi/cd lock c osc v ee clk_en v cc v ee v cc v cc v cc v cc v cc v cc v cc v cc v cc v cc v cc v cc v cc v cc v cc 4 x 75 see note 2 from gs9024 see note 1 to gs9020 to led driver (optional) 1.8k 15n 0.1 0.1 3.3p 365 (1%) 4.7n } 10k 75 37.5 75 10n 10n 75 100k pot (optional) 100p power supply decoupling capacitors are not shown. auto/man v ee 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 all resistors in ohms, all capacitors in microfarads, unless otherwise stated. notes 1. it is recommended that the ddi/ddi inputs are not driven when the sdi/sdi inputs are being used. this minimizes crosstalk between the ddi/ddi and sdi/sdi inputs and maximizes performance. 2. these resistors are not needed if the internal pull-up resistors on the gs9020 are used. 3. it is recommended that for new designs vco components should be returned to the r vco_rtn pin for improved ground bounce immunity. if replacing gs9025 with gs9025a connection to ground can be maintained. see note 3
522 - 75 - 05 18 of 18 gennum corporation mailing address: p.o. box 489, stn. a, burlington, ontario, canada l7r 3y3 tel. +1 (905) 632-2996 fax. +1 (905) 632-5946 shipping address: 970 fraser drive, burlington, ontario, canada l7l 5p5 gennum japan corporation shinjuku green tower building 27f, 6-14-1, nishi shinjuku, shinjuku-ku, tokyo, 160-0023 japan tel. +81 (03) 3349-5501, fax. +81 (03) 3349-5505 gennum uk limited 25 long garden walk, farnham, surrey, england gu9 7hx tel. +44 (0)1252 747 000 fax +44 (0)1252 726 523 gennum corporation assumes no responsibility for the use of any circuits described herein and makes no representations that the y are free from patent infringement. ? copyright june 2000 gennum corporation. all rights reserved. printed in canada. caution electrostatic sensitive devices do not open packages or handle except at a static-free workstation document identification data sheet the product is in production. gennum reserves the right to make changes at any time to improve reliability, function or design, in order to provide the best product possible. gs9025a revision notes: corrected input high level for a/d pin. for latest product information, visit www.gennum.com package dimensions 10.00 0.10 13.20 0.25 pin 1 10.00 0.10 0.80 bsc 0.45 max 0.30 min 13.20 0.25 2.20 max 1.85 min 0.35 max 0.15 min 2.55 max 0.23 max. 1.60 ref 0.3 max. radius 0.13 min. radius 0.88 nom. 0.20 min 5? to 16? 5? to 16? 7? max 0? min 0? min 44 pin mqfp all dimensions in millimetres

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